FIG. 1A illustrates the architecture of a conventional 1149.1 TAP circuit domain. The TAP domain includes a TAP controller, instruction register, set of data register including; (1) an internal scan register, (2) an in-circuit emulation (ICE) register, (3) an in-system programming (ISP) register, (4) a boundary scan register, and (5) a bypass register. Of the data registers, the boundary scan register and bypass register are defined by the IEEE 1149.1 standard. The other shown data registers are not defined by 1149.1, but can exist as data registers within the TAP domain. The TAP controller responds to the Test Clock (TCK) and Test Mode Select (TMS) signal inputs to coordinate serial communication through either the instruction register from Test Data In (TDI) signal to Test Data Out (TDO) signal, or through a selected one of the data registers from TDI to TDO. The Test Reset (TRST) signal input is used to initialize the TAP domain to a known state. The operation of the TAP domain is well known
FIG. 1B illustrates an IC or intellectual property core circuit incorporating the TAP domain and its TDI, TDO, TMS, TCK, and TRST interface. A core is a complete circuit function that is embedded within the substrate of an IC, such as a DSP or CPU core.
FIGS. 1C-1F illustrate the association between each of the data registers of FIG. 1A and the functional target circuit they connect to and access.
FIG. 2 illustrates the state diagram of the TAP controller of FIG. 1A. The TAP controller is clocked by the TCK input and transitions through the states of FIG. 2 in response to the TMS input. As seen in FIG. 2, the TAP controller state diagram consists of four key state operations, (1) a Reset/RunTest Idle state operation where the TAP controller goes to either enter a reset state, a run test state, or an idle state, (2) a Data or Instruction Scan Select state operation the TAP controller may transition through to select a data register (DR) or instruction register (IR) scan operation, or return to the reset state, (3) a Data Register Scan Protocol state operation where the TAP controller goes when it communicates to a selected data register, and (4) an Instruction Register Scan Protocol state operation where the TAP controller goes when it communicates to the instruction register. The operation of the TAP controller is well known.
FIG. 3 illustrates an example arrangement for connecting multiple TAP domains within an IC. Each TAP domain in FIG. 3 is similar to that shown and described in regard to FIG. 1A. While only one IC TAP domain exists in an IC, any number of core TAP domains (1-N) may exist within an IC. As seen in FIG. 3, the IC TAP domain and Core 1-N TAP domains are daisychained between the IC's TDI and TDO pins. All TAP domains are connected to the IC's TMS, TCK, and TRST signals and operate according to the state diagram of FIG. 2. During instruction scan operations, instructions are shifted into each TAP domain instruction register. One drawback of the TAP domain arrangement of FIG. 3 is that it does not comply with the IEEE 1149.1 standard, since, according to the rules of that standard, only the ICs TAP domain should be present between TDI and TDO when the IC is initially powered up. A second drawback of the TAP domain arrangement of FIG. 3 is that it may lead to unnecessarily complex access for testing, in-circuit emulation, and/or in-circuit programming functions associated with ones of the individual TAP domains.
For example, if scan testing is required on circuitry associated with the Core 1 TAP domain, each of the scan frames of the test pattern set developed for testing the Core 1 circuitry must be modified from their original form. The modification involves adding leading and trailing bit fields to each scan frame such that the instruction and data registers of the leading and trailing TAP domains become an integral part of the test pattern set of Core 1. Serial patterns developed for in-circuit emulation and/or in-circuit programming of circuitry associated with the TAP domain of Core 1 must be similarly modified. To overcome these and other drawbacks of the TAP arrangement of FIG. 3, the TAP arrangement of FIG. 4 was developed.
FIG. 4 illustrates a preferred structure for connecting multiple TAP domains within an IC according to U.S. Pat. No. 7,058,862. The structure includes input and output linking circuitry for connecting any one or more TAP domains to the IC's TDI, TDO, TMS, TCK and TRST pins or bond pads, and a TAP Linking Module (TLM) circuit for providing the control to operate the input and output linking circuitry. The combination of the input and output linking circuitry and TLM are hereafter referred to as the TLM architecture (TLMA). The concept of input and output linking circuitry and use of a TLM circuit to control the input and output linking circuitry was first disclosed in the referenced U.S. Pat. No. 7,058,862. The concept of the use of a TLM circuit was first disclosed in the referenced U.S. Pat. No. 6,073,254.
The input linking circuitry receives as input; (1) the TDI, TMS, TCK, and TRST signals on pins or bond pads of the IC, (2) the TDO outputs from the IC TAP (ICT) domain (TDOICT), the Core 1 TAP (C1T) domain (TDOC1T), and the Core N TAP (CNT) domain (TDOCNT), and (3) TAP link control input from the TLM. The TCK and TRST inputs pass unopposed through the input linking circuitry to be input to each TAP domain. The TMS input to the input linking circuitry is gated within the input linking circuitry such that each TAP domain receives a uniquely gated TMS output signal. As seen in FIG. 4, the IC TAP domain receives a gated TMSICT signal, the Core 1 TAP domain receives a gated TMSC1T signal, and the Core N TAP domain receives a gated TMSCNT signal. Example circuitry for providing the gated TMSICT, TMSC1T, and TMSCNT signals is shown in FIG. 5. In FIG. 5, the ENAICT, ENACIT, and ENACNT signals used to gate the TMSICT, TMSC1T, and TMSCNT signals, respectively, come from the TLM via the TAP link control bus.
From FIG. 5 it is seen that TMSCNT can be connected to TMS to enable the Core N TAP domain or be gated low to disable the Core N TAP domain, TMSC1T can be connected to TMS to enable the Core 1 TAP domain or be gated low to disable the Core 1 TAP domain, and TMSICT can be connected to TMS to enable the IC TAP domain or be gated low to disable the IC TAP domain. When a TAP domain TMS input (TMSCNT, TMSC1T, TMSICT) is gated low, the TAP domain is disabled by forcing it to enter the Run Test/Idle state of FIG. 2. A disabled TAP domain will remain in the Run Test/Idle state until it is again enabled by coupling it to the IC's TMS pin input as mentioned above. These methods of enabling TAP domains from the Run Test/Idle state and disabling TAP domains to the Run Test/Idle state was first disclosed in referenced U.S. Pat. No. 6,073,254.
The TDI, TDOCNT, TDOC1T, and TDOICT inputs to the input linking circuitry are multiplexed by circuitry within the input linking circuitry such that each TAP domain receives a uniquely selected TDI input signal. As seen in FIG. 4, the IC TAP domain receives a TDIICT input signal, the Core 1 TAP domain receives a TDIC1T input signal, and the Core N TAP domain receives a TDICNT input signal. Example circuitry for providing the TDIICT, TDIC1T, and TDICNT input signals is shown in FIG. 6.
In FIG. 6, the SELTDIICT, SELTDIC1T, and SELTDICNT control signals used to select the source of the TDIICT, TDIC1T, and TDICNT input signals, respectively, come from the TLM via the TAP link control bus. From FIG. 6 it is seen that TDICNT can be selectively connected to TDI, TDOC1T, or TDOICT, TDIC1T can be selectively connected to TDI, TDOCNT, or TDOICT, and TDIICT can be selectively connected to TDI, TDOCNT, or TDOC1T.
The output linking circuitry receives as input; (1) the TDOCNT output from the Core N TAP domain, the TDOC1T output from the Core 1 TAP domain, the TDOICT output from the IC TAP domain, and TAP link control input from the TLM. As seen in FIG. 4, the output linking circuitry outputs a selected one of the TDOCNT, TDOC1T, and TDOICT input signals to the TLM via the output linking circuitry TDO output. Example circuitry for providing the multiplexing of the TDOICT, TDOC1T, and TDOCNT signals to the TDO output is shown in FIG. 7.
In FIG. 7, the SELTDO control input used to switch the TDOICT, TDOC1T, or TDOCNT signals to TDO come from the TLM via the TAP link control bus. From FIG. 7 it is seen that any one of the TDOCNT, TDOC1T, and TDOICT signals can be selected as the input source to the TLM.
The TLM circuit receives as input the TDO output from the output linking circuitry and the TMS, TCK, and TRST IC input pin signals. The TLM circuit outputs to the IC's TDO output pin. From inspection, it is seen that the TLM lies in series with the one or more TAP domains selected by the input and output linking circuitry.
As described above, the TLM's TAP link control bus is used to control the input and output connection circuitry to form desired connections to one or more TAP domains so that the one of more TAP domains may be accessed via the IC's TDI, TDO, TMS, TCK, and TRST pins. The TAP link control bus signals are output from the TLM during the Update-IR state of the IEEE TAP controller state diagram of FIG. 2.
FIG. 8A illustrates in detail the structure of the TLM. The TLM consists of a TAP controller, instruction register, multiplexer, and 3-state TDO output buffer. The TAP controller is connected to the TMS, TCK and TRST signals. The TDI input is connected to the serial input (I) of the instruction register and to a first input of the multiplexer. The serial output (O) of the instruction register is connected to the second input of the multiplexer. The parallel output of the instruction register is connected to the TAP link control bus of FIG. 4. The output of the multiplexer is connected to the input of the 3-state buffer. The output of the 3-state buffer is connected to the IC TDO output pin. The TAP controller outputs control (C) to the instruction register, multiplexer, and 3-state TDO output buffer. The TAP controller responds to TMS and TCK input as previously described in regard to FIGS. 1A and 2. During instruction scan operations, the TAP controller enables the 3-state TDO buffer and shifts data through the instruction register from TDI to TDO. During data scan operations, the TAP controller enables the 3-state TDO buffer and forms a connection, via the multiplexer, between TDI and TDO.
FIG. 8B illustrates the instruction register in more detail. The instruction register consists of a shift register, TAP link decode logic, and update register. The shift register has a serial input (I), a serial output (O), a control (C) inputs, a parallel output, and a parallel input. The parallel input is provided for capturing fixed logic 0 and 1 data bits into the first two bit positions shifted out on TDO during instruction scan operations, which is a requirement of the IEEE 1149.1 standard. The parallel output from the instruction register is input to TAP link decode logic. The parallel output from the TAP link decode logic is input to the update register. The parallel output of the update register is the TAP link control bus input to the input and output linking circuitry. During the Capture-IR state of FIG. 2, the shift register captures data (0 & 1) on the parallel input, During the Shift-IR state of FIG. 2, the shift register shifts data from TDI (I) to TDO (O). During the Update-IR state of FIG. 2, the update register loads the parallel input from the TAP link decode logic and outputs the loaded data onto the TAP link control bus.
FIG. 9 illustrates various possible link arrangements Link0-Link6 of TAP domain connections during 1149.1 instruction scan operations using the TLMA. Since during instruction scan operations, the TLM's instruction register is physically present and in series with the connected TAP domain(s) instruction register(s), the instruction scan frame for each link arrangement will be augmented to include the TLM's instruction register bits. The concept of augmenting the length of TAP domain instruction registers with a TLM's instruction register was first disclosed in referenced U.S. Pat. No. 6,324,662. In this example, the TLM's instruction shift register of FIG. 8B is 3 bits long and the 3 bit instructions (000-110) are decoded by the TAP link decode logic of FIG. 8B to uniquely select a different TAP domain connection link arrangement between the ICs TDI and TDO pins. Shifting in the following 3 bit TLM instructions and updating them from the TLM to be input to the input and output linking circuitry will cause the following TAP domain link connections to be formed.
A Link0 “000” instruction shifted into and updated from the TLM instruction register will cause the IC TAP domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
A Link1 “001” instruction shifted into and updated from the TLM instruction register will cause the IC TAP domain and the Core 1 TAP Domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
A Link2 “010” instruction shifted into and updated from the TLM instruction register will cause the IC TAP domain and the Core N TAP Domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
A Link3 “011” instruction shifted into and updated from the TLM instruction register will cause the IC TAP domain, the Core 1 TAP Domain, and the Core N TAP domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
A Link4 “100” instruction shifted into and updated from the TLM instruction register will cause the Core 1 TAP Domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
A Link5 “101” instruction shifted into and updated from the TLM instruction register will cause the Core 1 TAP Domain and Core N TAP domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
A Link6 “110” instruction shifted into and updated from the TLM instruction register will cause the Core N TAP Domain to be enabled and connected in series with the TLM between the TDI and TDO IC pins.
At power up of the IC, the TLM 3-bit instruction shall be initialized to “000” to allow the IC TAP domain Link0 arrangement to be enabled and coupled between TDI and TDO. This complies with the IC power up requirement established in the IEEE 1149.1 standard. The process of powering up a multiple TAP domain IC to where only the IC TAP domain is enabled and selected between the IC's TDI and TDO pins was first disclosed in referenced U.S. Pat. No. 6,073,254. Following power up, an instruction scan operation can be performed to shift instruction data through the IC TAP domain and the serially connected TLM to load a new IC TAP domain instruction and to load a new 3 bit link instruction into the TLM. If the power up IC TAP domain Link0 arrangement is to remain in effect between TDI and TDO, the 3 bit “000” TLM instruction of FIG. 9 will be re-loaded into the TLM instruction register during the above mentioned instruction scan operation. However, if a new TAP domain link arrangement is desired between TDI and TDO, a different 3 bit TLM link instruction will be loaded into the TLM instruction register during the above mentioned instruction register scan operation.
FIG. 10 is provided to illustrate that during 1149.1 data scan operations the TLM is configured, as described in regard to FIG. 8A, to simply form a connection path between the output of the selected TAP domain link arrangement Link0-Link6 and the IC's TDO pin. Thus the TLM does not add bits to 1149.1 data scan operations as it does for 1149.1 instruction scan operations.